1. Field of the Invention
The invention relates generally to integrated circuits having repeated logic and interconnect structures provided therein. The invention relates more specifically to the problem of selecting the numbers and types of interconnect resources to be provided within an integrated circuit monolith that contains a field programmable gate array (FPGA).
2a. Cross Reference to Related Applications
The following co-pending U.S. patent applications(s) are related to the present application and their disclosures are incorporated herein by reference:
(A) Ser. No. 08/948,306 filed Oct. 9, 1997 by Om P. Agrawal et al. and originally entitled, "VARIABLE GRAIN ARCHITECTURE FOR FPGA INTEGRATED CIRCUITS"; PA1 (B) Ser. No. 08/996,361 filed Dec. 22, 1997, by Om Agrawal et al. and originally entitled, "SYMMETRICAL, EXTENDED AND FAST DIRECT CONNECTIONS BETWEEN VARIABLE GRAIN BLOCKS IN FPGA INTEGRATED CIRCUITS"; PA1 (C) Ser. No. 08/995,615 filed Dec. 22, 1997, by Om Agrawal et al. and originally entitled, "A PROGRAMMABLE INPUT/OUTPUT BLOCK (IOB) IN FPGA INTEGRATED CIRCUITS"; PA1 (D) Ser. No. 08/995,614 filed Dec. 22, 1997, by Om Agrawal et al. and originally entitled, "INPUT/OUTPUT BLOCK (IOB) CONNECTIONS TO MAXL LINES, NOR LINES AND DENDRITES IN FPGA INTEGRATED CIRCUITS"; PA1 (E) Ser. No. 08/995,612 filed Dec. 22, 1997, by Om Agrawal et al. and originally entitled, "FLEXIBLE DIRECT CONNECTIONS BETWEEN INPUT/OUTPUT BLOCKS (IOBs) AND VARIABLE GRAIN BLOCKS (VGBs) IN FPGA INTEGRATED CIRCUITS"; PA1 (F) Ser. No. 08/997,221 filed Dec. 22, 1997, by Om Agrawal et al. and originally entitled, "PROGRAMMABLE CONTROL MULTIPLEXING FOR INPUT/OUTPUT BLOCKS (IOBs) IN FPGA INTEGRATED CIRCUITS"; PA1 (G) Ser. No. 08/996,049 filed Dec. 22, 1997 by Om P. Agrawal et al. and originally entitled, "DUAL PORT SRAM MEMORY FOR RUN-TIME USE IN FPGA INTEGRATED CIRCUITS; PA1 (H) Ser. No. 09/008,762 filed Jan. 19, 1998 by Om P. Agrawal et al. and originally entitled, "SYNTHESIS-FRIENDLY FPGA ARCHITECTURE WITH VARIABLE TIMING INTERCONNECT"; PA1 (H) Ser. No. 09/187,689 filed Nov. 5, 1998 by Om P. Agrawal et al. and originally entitled, "TILEABLE AND COMPACT LAYOUT FOR SUPER VARIABLE GRAIN BLOCKS WITHIN FPGA DEVICE". PA1 (A) U.S. Pat. No. 5,212,652 issued May 18, 1993 to Om Agrawal et al, (filed as Ser. No. 07/394,221 on Aug. 15, 1989) and entitled, PROGRAMMABLE GATE ARRAY WITH IMPROVED INTERCONNECT STRUCTURE; PA1 (B) U.S. Pat. No. 5,621,650 issued Apr. 15, 1997 to Om Agrawal et al, and entitled, PROGRAMMABLE LOGIC DEVICE WITH INTERNAL TIME-CONSTANT MULTIPLEXING OF SIGNALS FROM EXTERNAL INTERCONNECT BUSES; and PA1 (C) U.S. Pat. No. 5,185,706 issued Feb. 9, 1993 to Om Agrawal et al.
2b. Cross Reference to Related Patents
The following U.S. patent(s) are related to the present application and their disclosures are incorporated herein by reference:
3. Description of Related Art
As the density of digital logic circuitry within integrated circuits (IC's) increases, and as the signal-processing speed of such logic also increases, the ability of interconnect to route all signals in timely fashion between spaced-apart logic sections (e.g., CLB's) becomes more problematic and more important to proper operation of the integrated circuit.
Physical layout of logic sections within each logic area of an IC device may play a critical role in defining the signal-processing speed of the overall IC device. Device performance may also be affected by the physical separation between critical logic sections. Device performance may be further affected by the interplay between interconnect resource allocation and logic resource allocation.
More specifically, when it comes to the field of programmable logic arrays, artisans have begun to recognize that conductors of different lengths, orientations, and other attributes should be provided for servicing different kinds of signals. By way of example, a first class of relatively long, low resistance conductors may be provided for broadcasting common control signals (e.g., clock, clock enable, etc.) over relatively large distances of the IC device with minimal skew. Such special conductors are sometimes referred to as low-skew longlines.
Artisans have also begun to realize that significantly shorter wire segments may be advantageously dedicated for transmitting logic input and logic output signals between immediately adjacent logic sections. These dedicated conductors are sometimes referred to as direct-connect lines.
At the same time, artisans wish to provide field programmable logic array devices with general-purpose conductors and general-purpose routing switches (or routing switch boxes) for carrying out general-purpose, programmable routing of signals. It is desirable to have FPGA's that can be configured to efficiently accommodate a wide variety of to-be-implemented designs. The variety of designs can span a taxonomic universe that includes `random logic` at one end, highly-ordered data-path structures at the other end, and intermediately-ordered control logic structures in between.
The evolution in the art of FPGA's toward using both general purpose and special purpose conductors within the interconnect portion of logic arrays should mesh with a concurrent and general evolution affecting logic circuits per se. The logic circuitry of logic array IC's is consistently evolving towards faster signal processing speeds and greater per area densities of logic functionalities. On one hand, artisans wish to provide field programmable logic arrays with as much logic functionality as is usefully possible. On the other hand, artisans wish to provide in such FPLA's as much flexible interconnect capability as is usefully possible.
At some point, the amount of logic functionality that is provided begins to compete for limited space within the IC device with the amount of interconnect functionality that is also provided in the same device.
This conflict creates a need for properly selecting the numbers and types of interconnect resources that are provided or not provided within the IC device. Types and numbers of interconnect resources of each type should be tailored so as to efficiently mesh with the densities of the logic functionalities that are provided in the same IC device. The types and numbers of interconnect resources of each type should also be tailored so as to efficiently accommodate variations in design specification with respect to the timing and processing of broadcast control signals, of high-speed local signals, and also of randomly-routed, general purpose signals.